1. Field of the Invention
The present invention relates to a voltage regulator and a method of controlling a voltage regulator.
2. Description of the Related Art
A voltage regulator stably supplies a constant voltage from an output terminal thereof even if an output current thereof is changed by a load change or the like.
However, if a significant load change occurs to cause an excessive overshoot voltage at the output terminal, or if a short-circuit is caused by connection between the output terminal and a power source terminal (hereinafter sometimes referred to as “a power supply short-circuit”), the gate voltage of an input transistor in a differential amplifier circuit of the voltage regulator connected to the output terminal rises. In view of preventing the gate of the input transistor from breaking down, the voltage regulator may include a circuit configuration in which, even if an overshoot occurs at the output terminal or a short-circuit is caused by connection with the power source terminal, an excessive rise in the gate voltage of the input transistor is inhibited to prevent the gate of the input transistor from breaking down (see, for example, Japanese Patent Application Laid-open No. 2015-138394).
FIG. 9 is a circuit diagram illustrating a configuration example of a conventional voltage regulator described in Japanese Patent Application Laid-open No. 2015-138394. With referring to FIG. 9, a diode 121 is connected between a gate and a source of a PMOS transistor as a first input transistor 111 in a differential amplifier circuit. If an overshoot occurs at an output terminal 120, the arrangement of the diode 121 allows an electric current to flow from the output terminal 120 to the ground of a voltage regulator through a resistor 116, the diode 121, a second input transistor 109, and an NMOS transistor 108. Thus, the gate voltage of the first input transistor 111 can be reduced until a voltage difference between the gate voltage and a voltage at a connection point P1 corresponds to a forward voltage of the diode 121.
In the conventional voltage regulator, it is possible to inhibit the gate of the first input transistor 111 from breaking down due to an overshoot at the output terminal 120.
However, in the conventional voltage regulator, if the voltage at the output terminal 120 drops due to a short-circuit caused by connection with the ground terminal GND (hereinafter sometimes referred to as “a ground short-circuit”, bias temperature instability (BTI) differently affects the first input transistor 111 and the second input transistor 109 in a differential amplifier circuit 151, thus causing an offset in an output voltage from the output terminal 120.
In the following, with reference to FIG. 9, description is given of the offset caused in the output voltage if the voltage at the output terminal 120 drops. A reference voltage VREF is applied from a constant voltage source 110 and is applied to the gate of the second input transistor 109.
If the voltage at the output terminal 120 drops, a gate voltage VFB of the first input transistor in the differential amplifier circuit drops to a level in the vicinity of that of a ground voltage.
Consequently, the gate voltage of the input first transistor 111 drops to a level significantly smaller than that of the reference voltage VREF applied to the gate of the second input transistor 109, and substantially the entire drain current (tail current) flows from the PMOS transistor 105 into the first input transistor 111.
The respective gate-source voltages of the first and second input transistors 111 and 109 in the case described above are represented by Vgs(111) and Vgs(109) given below.Vgs(111)≈Vth(111)Vgs(109)=VREF−|Vgs(111)|
In consideration of the respective gate-source voltages Vgs(111) and Vgs(109), the second input transistor 109 is affected by positive bias temperature instability (PBTI).
The first transistor 111 is affected by negative bias temperature instability (NBTI).
If the voltage drop at the output terminal 120 continues over a long period of time, an amount of variation in threshold voltage of the second input transistor 109 under the influence of the PBTI is different from an amount of variation in threshold voltage of the first input transistor 111 under the influence of the NBTI. In the first input transistor 111, the gate-source voltage Vgs(111) applied to the gate is approximate to the threshold voltage, and the threshold voltage variation is accordingly less affected by the NBTI.
Thus, while the respective threshold voltages of input transistors 111 and 109 are the same during manufacturing, the respective amounts of variation in threshold voltage described above are different. Consequently, the input transistors 111 and 109 have different threshold voltages.
In the differential amplifier circuit, due to imbalance between the threshold voltages, differential amplification of the reference voltage VREF and an output voltage VOUT is normally performed. In accordance with the voltage difference between the threshold voltages, an offset occurs in the output voltage, resulting in that the output voltage corresponding to the reference voltage cannot be obtained.